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A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS

Sung, BRS; Jo, DS; Jang, IH; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25

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