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Showing results 1 to 4 of 4

1
32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM

Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp.442 - 444, IEEE, 2021-02-13

2
A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02

3
A-58dBc-Worst-Fractional-Spur and-234dB-FoM(jitter), 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word

Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Lee, Jeonghyun; Park, Hangi; Lee, Kyuho Jason; Choi, Jaehyouk, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.270 - 272, Institute of Electrical and Electronics Engineers Inc., 2020-02-19

4
An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS

Yoo, Seyeon; Park, Suneui; Choi, Seojin; Cho, Yoonseo; Yoon, Heein; Hwang, Chanwoong; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), IEEE, 2021-02-13

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