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Showing results 1 to 3 of 3

1
A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

Hong, Hyeok-Ki; Kang, HW; Jo, DS; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25

2
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control

Hong, Hyeok-Ki; Kim, Wan; Park, Sun-Jae; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, 2012 IEEE Custom Integrated Circuits Conference, IEEE, 2012-09-10

3
An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement

Hong, Hyeok-Ki; Kang, Hyun-Wook; Sung, Barosaim; Lee, Choong-Hoon; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, 2013 IEEE International Solid-State Circuits Conference, IEEE, 2013-02-20

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