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Showing results 1 to 13 of 13

1
A fast locking time ADPLL using temperature variation compensated lookup table

Choi, HaeWook, TriSAI 2009, pp.101 - 104, 2009

2
A metastability free retiming logic of ADPLL

Choi, HaeWook, ITC-CSCC 2009, pp.1526 - 1528, 2009

3
Adaptive motion estimation algorithm using spatial and temporal correlation

Lim, J.-H.; Choi, HaeWook, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 2001), pp.473 - 476, 2001-08-26

4
An optimum mapping of IPs for On-Chip Network design based on the minimum latency constraint

Ngo, V.-D.; Choi, HaeWook, TENCON 2005 - 2005 IEEE Region 10 Conference, v.2007, 2005-11-21

5
An QoS aware mapping of cores onto NoC architectures

Nguyen, H.-N.; Ngo, V.-D.; Bae, Y.; Cho, H.; Choi, HaeWook, 5th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2007, pp.278 - 288, 2007-08-29

6
Assessing routing behavior on on-chip-network

Nguyen, H.-N.; Ngo, V.-D.; Choi, HaeWook, 2006 International Conference on Computer Engineering and Systems, ICCES'06, pp.62 - 65, 2006-11-05

7
Latency optimization for NoC design of H.264 decoder based on self-similar traffic modeling

Ngo, V.-D.; Chang, J.-Y.; Bae, Y.; Cho, H.; Choi, HaeWook, 5th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2007, pp.289 - 302, 2007-08-29

8
Multiplane virtual channel router for network-on-chip design

Noh, S.; Ngo, V.-D.; Jao, H.; Choi, HaeWook, HUT-ICCE 2006 1st International Conference on Communications and Electronics, pp.348 - 351, 2006-10-10

9
On chip network: Topology design and evaluation using NS2

Ngo, V.-D.; Choi, HaeWook, 7th International Conference on Advanced Communication Technology, ICACT 2005, v.2, pp.1292 - 1295, 2005-02-21

10
Performance and complexity analysis of credit-based end-to-end flow control in network-on-chip

Noh, S.; Kim, D.; Ngo, V.-D.; Choi, HaeWook, 5th International Symposium on Parallel and Distributed Processing and Applications, ISPA 2007, pp.268 - 277, 2007-08-29

11
Realization of video object plane decoder on mesh on-chip network architecture

Nguyen, H.-N.; Ngo, V.-D.; Choi, HaeWook, Third IASTED International Conference on Circuits, Signals, and Systems, CSS 2005, pp.137 - 141, 2005-10-24

12
Realizing network on chip design of H.264 decoder based on throughput aware mapping

Ngo, V.-D.; Nguyen, H.-N.; Choi, HaeWook, HUT-ICCE 2006 1st International Conference on Communications and Electronics, pp.337 - 342, 2006-10-10

13
The optimized tree-based network on chip topologies for H.264 decoder design

Ngo, V.-D.; Choi, HaeWook; Bae, Y.; Cho, H., 2006 International Conference on Computer Engineering and Systems, ICCES'06, pp.343 - 347, 2006-11-05

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