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Showing results 1 to 6 of 6

1
A 550μW 10b 40MS/s SAR ADC with multistep addition-only digital error correction

Cho, S.-H.; Lee, C.-K.; Kwon, J.-K.; Ryu, Seung-Tak, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, pp.561 - 564, IEEE, 2010-09-19

2
A cognitive control architecture for an artificial creature using episodic memory

Kuppuswamy, N.S.; Cho, S.-H.; Kim, Jong-Hwan, 2006 SICE-ICASE International Joint Conference, pp.3104 - 3110, 123, 2006-10-18

3
A time-interleaved flash-SAR architecture for high speed A/D conversion

Sung, B.R.S.; Cho, S.-H.; Lee, C.-K.; Kim, J.-I.; Ryu, Seung-Tak, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, pp.984 - 987, IEEE, 2009-05-24

4
Behavior selection and memory-based learning for artificial creature using two-layered confabulation

Cho, S.-H.; Kim, Y.-H.; Park, I.-W.; Kim, Jong-Hwan, 16th IEEE International Conference on Robot and Human Interactive Communication, 2007, pp.992 - 997, IEEE, 2007-08-26

5
Nonlinear slip dynamics for an omniwheel mobile robot platform

Stonier, D.; Cho, S.-H.; Choi, S.-L.; Kuppuswamy, N.S.; Kim, Jong-Hwan, 2007 IEEE International Conference on Robotics and Automation, ICRA'07, pp.2367 - 2372, IEEE, 2007-04-10

6
Software robot in a PDA for human interaction and seamless service

Kim, Y.-H.; Cho, S.-H.; Choi, S.-H.; Kim, Jong-Hwan, 16th IEEE International Conference on Robot and Human Interactive Communication, RO-MAN, pp.968 - 973, IEEE, 2007-08-26

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