Showing results 4 to 6 of 6
Multi-thread VLIW processor architecture for HDTV decoding Kim, H; Yang, WS; Shin, MC; Min, SJ; Bae, SO; Park, In-Cheol, CICC 2000: 22nd Annual Custom Integrated Circuits Conference, pp.559 - 562, CICC, 2000-05-21 |
Optimal down-conversion in compressed DCT domain with minimal operations Shin, MC; Park, In-Cheol, Visual Communications and Image Processing 2000, pp.1613 - 1620, SPIE, 2000-06-20 |
Programmable Turbo Decoder Supporting Multiple Third-Generation Wireless Standards 박인철; Shin, MC, SOC Design Conference, 2002-10 |
Discover