Showing results 2 to 5 of 5
A 120mW embedded 3D graphics rendering engine with 6Mb logically local frame-buffer and 3.2GByte/s run-time reconfigurable bus for PDA-chip Woo, R.; Yoon, C.-W.; Kook, J.; Lee, S.-J.; Lee, K.; Park, Y.-H.; Yoo, Hoi-Jun, 2001 VLSI Circuits Symposium, pp.95 - 98, IEEE, 2001-06-14 |
A 80/20MHz 160mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications Yoon, C.-W.; Woo, R.; Kook, J.; Lee, S.-J.; Lee, K.; Bae, Y.-D.; Park, In-Cheol; et al, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.142 - 143441, 2001-02-05 |
A Comparative Analysis of a DDR-SDRAM and a D-RDRAM usind a POPeye Simulator Yoo, Hoi-Jun; Lee, K.; Yoon, C.W.; Woo, R.; Kook, J., IEEE International Symposium on Circuits and Systems, pp.v81 - v84, IEEE, 2001 |
Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications Yoon, C.-W.; Kook, J.; Woo, R.; Lee, S.-J.; Lee, K.; Yoo, Hoi-Jun, 2001 VLSI Circuits Symposium, pp.99 - 102, IEEE, 2001-06-14 |
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