DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Yang, Tae-Yong | - |
dc.contributor.advisor | 양태용 | - |
dc.contributor.author | Kim, Se-Jung | - |
dc.contributor.author | 김세정 | - |
dc.date.accessioned | 2011-12-14T04:07:59Z | - |
dc.date.available | 2011-12-14T04:07:59Z | - |
dc.date.issued | 2006 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=255389&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/40737 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 산업공학과, 2006.2, [ ii, 41 p. ] | - |
dc.description.abstract | This paper mainly deals with the problem determining workloads in a semiconductor fabrication line. A mathematical model is proposed to determine the amount and type of wafers which will be processed on equipment used in photolithography process. Photolithography process is main bottleneck process in the fabrication line, especially on the steppers. It is assumed that this stepper process is the most significant bottleneck process and others are non-bottleneck processes It is the goal of the proposed MIP model to control WIP level in the buffer of stepper to the target WIP level considering the setup time The ratio test between imbalance of actual WIP to the target WIP and setup time in the objective function was performed, and hence the most reasonable ratio was proposed. This test was performed using OPL Studio. Because of the long computation time of MIP model, it is necessary to suggest heuristic methods. LP relaxation and two direct stepper allocation methods are suggested. Among them LP relaxation method gives the solution near the optimal solution. The difference between optimal solution and the solution of LP relaxation is less than 10%. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | setup time | - |
dc.subject | heurtistic | - |
dc.subject | MIP | - |
dc.subject | OR | - |
dc.subject | semiconductor | - |
dc.subject | fabrication line | - |
dc.subject | WIP | - |
dc.subject | production control | - |
dc.subject | 정수계획법 | - |
dc.subject | 선형계획법 | - |
dc.subject | 발견적 기법 | - |
dc.subject | 셋업 시간 | - |
dc.subject | 생산 | - |
dc.subject | 반도체 | - |
dc.subject | LP | - |
dc.subject | 재공재고 | - |
dc.title | (A) study on the production control policies considering WIP balance and setup time in a semiconductor fabrication line | - |
dc.title.alternative | 반도체 생산 공정에서 재공재고 균형과 셋업 시간을 고려한 생산 계획 연구 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 255389/325007 | - |
dc.description.department | 한국과학기술원 : 산업공학과, | - |
dc.identifier.uid | 020033103 | - |
dc.contributor.localauthor | Yang, Tae-Yong | - |
dc.contributor.localauthor | 양태용 | - |
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