Production planning and control in semiconductor wafer fabrication and probing facilities = 반도체 웨이퍼 제조공정과 프로브공정의 생산 계획 작성 및 통제에 관한 연구

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This dissertation focuses on production planning and control problems in a semiconductor wafer fabrication and probing facilities which produces semiconductor products of a large number of different product types in a low-volume and high-variety setting. In these fabs and probing facilities, it is not easy to achieve both meeting due dates of orders and increasing production efficiency because the production environment is very complicated due to complex configuration such as reentrant and various resource constraints. Therefore, it is required to develop new production planning and control methodologies that improve the production cost and the tardiness of customers’ orders. In this dissertation, we suggest a production planning method for obtaining feasible and efficient production plan and propose the lot merging/splitting algorithms in the fab to improve the production efficiency with limited resource. Then, we develop a production scheduling methodologies and lot transfer methodology for multiple lines of probing facilities. First, we consider a production planning and scheduling problem in a semiconductor wafer fabrication facility. We propose a two-level hierarchical production planning method that employs an iterative procedure for production planning and operations scheduling. In the method, production plans are obtained with a linear programming model in the aggregate level, and schedules at the machines are obtained with a priority-rule-based scheduling method and evaluated with discrete-event simulation in the disaggregate level. An iterative scheme is adopted for obtaining a good and feasible production plan. Secondly, we consider a lot merging/splitting problem in a semiconductor wafer fabrication facility in which a relatively large number of wafer types are produced according to orders with different due dates. In the fab, two or more lots can be merged into a single lot if routes and all processing conditions of the lots are the same for ...
Kim, Yeong-Daeresearcher김영대researcher
한국과학기술원 : 산업및시스템공학과,
Issue Date
327721/325007  / 020045112

학위논문(박사) - 한국과학기술원 : 산업및시스템공학과, 2009. 8., [ viii, 128 p. ]


Production Planning; Scheduling; Semiconductor; fabrication; probing; 생산계획; 생산일정; 반도체; 웨이퍼제작; 웨이퍼프로브; Production Planning; Scheduling; Semiconductor; fabrication; probing; 생산계획; 생산일정; 반도체; 웨이퍼제작; 웨이퍼프로브

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