(An) ultra compact CMOS transceiver for HF multi-standard RFID system

Abstract

In this thesis, a HF RFID multi-standard transceiver is proposed. Before designing the system, an analysis of RFID standards is processed. The block level system is designed and verified via test board composed of commercial components. The designed system is also tested with a commercial tag. Based on test result analysis, each block of system is then designed. For maintaining multi-standard, the transmitter is composed of ASK modulator with varied modulation indexes and power control unit which can adjust the recognition range. The receiver consists of an envelope detector, variable gain amplifier (VGA), low pass filter (LFP), and a 1-bit ADC. The designed HF RFID transceiver was fabricated using Chartered 0.18 $\mum$ CMOS process. By using commercial tag, integrated chip and evaluation board, we could operate the tag and read the unique information of the commercial tag. Next, the measurement of designed HF RFID transceiver is reviewed. We find the points to be revised. Based on these analysis results, the transmitter is made with a partial revision and the new architecture of receiver is proposed. This revised transceiver is more efficient and smaller than the pre-designed transceiver. The transmitter part is composed of an ASK modulator, a mode selector, and a power controller, like the pre-designed transmitter. In the receiver, many of the parts are revised. This consists of a half-wave rectifier, an envelope detector using a supply-independent biasing circuit, and an adjustable Schmitt trigger. The new designed structure will be fabricated using TSMC 0.18 $\mum$ CMOS technology.