To cope with the increasing demand of high throughput MAC system, this dissertation presents an enhanced MAC implementation architecture and its FPGA (Field Programmable Gate Array) implementation of IEEE802.11ac VHT PHY based WLAN system with near-theoretical throughput performance of 1.18Gbps at 1.75Gbps PHY rate. The implemented system is based on the IEEE 802.11n MAC protocol which supports SW based reconfigurable features. For an efficient and optimal design procedure, we analyzed the latency and throughput bottlenecks of the of the IEEE 802.11e/n MAC, and verified the throughput enhancement using SystemC based TLM (Transaction Level Modeling) simulation. It is verified that the throughput difference between TLM simulation and hardware measurement is less than 5%. The implementation results show that the video access category (AC) packet could be transmitted with the MAC throughput of 1.078Gbps, given the PHY rate of 1.75Gbps, achieving the MAC efficiency of 60.3%. Also the resource usage of the proposed MPSoC based system architecture is about 8% utilization at the Xilinx Virtex5LX330 FPGA prototyping board.
Apart from high throughput MAC features, this thesis also presented reconfigurable real-time link adaptation and scheduling scheme. A lot of modulation and coding rate (MCS) combination, MIMO mode, or fragmentation/aggregation scheduling scheme can be applied for the multiple-input multiple-out (MIMO) technology. Because such kind of scheduling scheme is closely related to the signal-to-noise ratio or channel condition, we presented cross-layer based rate adaptation scheme. The SNR and BER information of the physical layer is referenced to the scheduling strategy in MAC layer. This dissertation contains real operational functional HW blocks of physical layer and MAC layer with corresponding rate adaptation scheme. An application guideline to apply rate adaptation to the implemented MAC is also outlined in this thesis.