Power Efficient Algorithms for SAR ADCs

Abstract

Two asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) with power efficient algorithms are presented. For the first ADC, straightforward digital-to-analog converter (DAC) control removes the switch-back operation in traditional SAR ADC and saves DAC switching power consumption. The metastable-then-set (MTS) algorithm further reduces power consumption by finishing the conversion when the metastability is detected. Interference between two asynchronous ADCs sharing a common reference is minimized by the flag-synchronization method. For the other 10b SAR ADC, three virtually divided sub-DACs have a 0.5 LSB over-range between stages owing to additional decision phases incorporating DAC rearrange only. These redundancies make it possible to guarantee 10b linearity with a 37% speed enhancement under a 4b-accurate DAC settling condition at MSB decision. This algorithm is called as multistep addition-only digital error correction (ADEC). Two ADCs have been implemented in a CMOS $0.13\mum$ technology and operate under 1.2V supply. At a sampling rate of 17.5MS/s and 40MS/s, the chips achieve a peak SNDR of 51.3dB and 50.6dB, respectively. The measured total power dissipation is $438\muW$ and $550\muW$, and their FOMs are 79fJ/conv.step and 42fJ/conv.step.