Circuit extraction from MOS/LSI mask layout

Abstract

This thesis describes CIREX (CIRcuit Extractor), an automated circuit extraction program that computes circuit connectivity and transistor dimensions. In addition, it computes substrate capacitances and parasitic resistances. The extracted circuit is therefore suitable for use in timing analysis and detailed circuit simulation. CIREX uses point-to-point extraction algorithm to calculate the interconnection resistances and substrate capacitances. This algorithm can be replaced by node extraction algorithm for the worst-case timing analysis of the circuit. The output format of circuit information extracted by CIREX is the same as SPICE2 input syntax. CIREX can be used to extract circuit information from n-well CMOS and p-well CMOS layout.