Gate and functional level logic simulation with 8-state signal model

Abstract

Conventional logic simulators are mostly designed for simulating bipolar devices and hence they are not suitable for simulating modern MOS circuits. Also, conventional gate-level simulators are inadequate for handling large digital networks. In this thesis, is presented a gate and functional level logic simulation with an 8-state signal model, which can simulate almost any kind of systems and/or IC including MOS devices. Owing to the use of an accurate and reasonable signal model with 8-states, the developed simulator can easily simulate standard gates, MOS high impedance logic states, race, TRI-state buffer and BUS structures. It can also handle several functional elements such as counters, memory-elements, shift registers, etc. The simulator was tested for a number of practical logic circuits to verify its proper performance.