Gate and functional level logic simulation with 8-state signal model8-상태의 신호 모델을 이용한 게이트 및 기능 레벨의 논리 시뮬레이션

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Conventional logic simulators are mostly designed for simulating bipolar devices and hence they are not suitable for simulating modern MOS circuits. Also, conventional gate-level simulators are inadequate for handling large digital networks. In this thesis, is presented a gate and functional level logic simulation with an 8-state signal model, which can simulate almost any kind of systems and/or IC including MOS devices. Owing to the use of an accurate and reasonable signal model with 8-states, the developed simulator can easily simulate standard gates, MOS high impedance logic states, race, TRI-state buffer and BUS structures. It can also handle several functional elements such as counters, memory-elements, shift registers, etc. The simulator was tested for a number of practical logic circuits to verify its proper performance.
Advisors
Park, Song-Bai박송배
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1983
Identifier
63762/325007 / 000811014
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1983.2, [ 1책(면수복잡) ]

URI
http://hdl.handle.net/10203/39615
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=63762&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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