Implementation of a multi-rate speech digitizer

Abstract

In this thesis implementation of a very compact and efficient multi-rate vocoder with variable transmission rates of 2.4, 4.8, 9.6 and 15 kbits/s is studied. The overall algorithm of the multi-rate vocoder has been made by slightly modifying the residual-excited linear prediction (RELP) vocoder with the transmission rate of 9.6 kbits/s. The residual encoder employed in the RELP vocoder uses hybrid companding delta modulation (HCDM). This HCDM is used also as a 15 kbits/s coder. If the residual is downsampled before encoding, we can realize a 4.8 kbit/s coder. If the residual encoder is not used, we can realize the system as 2.4 kbit/s coder by incorporating a pitch extractor. In the 4.8 kbits/s coder a pitch predictive loop is used to compensate for the degradation of speech quality due to the downsampling of residual. In a conventional RELP system spectral flattening is done to generate the excitation signal to the synthesizing filter. We have also tested the pitchimplanted residual excitation method to generate the hybrid excitation signal to the synthesizing filter. Hardware implementation has been carried out in three steps. First the multirate vocoder algorithm has been formulated and its parameters has been optimized by real simulation. Second, the algorithm has been tested using 16-bit fixed point arithmetic by integer simulation. Finally, the multi-rate algorithm has been implemented in hardware using bit-slice microprocessors.