Performance analysis of modified digital costas loop

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A new type of digital phase-locked loop(DPLL) that employs a phase error detector with linear characteristic is proposed and analyzed for the first-and second-order loops in the absence and presence of noise. By inserting the function $\tan^{-1}(\cdot)$ in the loop, the DPLL phase error detector characteristic becomes linear. Consequently, the system equation describing the behavior of the loop is also linear. In the absence of noise, the first-and second-order loops have been analyzed by plotting the phase planes. Also, the false lock and oscillation phenomena occurring under some initial conditions have been considered. In addition, the locking range for the DPLL to achieve exact locking independently of initial conditions is obtained in a closed form for the firstand second- order systems. These results are verified by computer simulation. In the presence of noise, the loop is analyzed by solving Chapmann-Kolmogorov(C-K) equation. The steady state probability density function(pdf) of the phase error has been obtained by solving the C-K equation numerically. The mean and variance of the phase error in the steady state have been obtained analytically, and are compared with the results obtained by computer simulation. Finally, the conditions that cycle slipping occurs have been derived for the first-and second-order loops mathematically. The probability of cycle slipping has been obtained by computer simulation for the first- and second-order loops.
Advisors
Un, Chong-Kwanresearcher은종관researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1980
Identifier
62713/325007 / 000781187
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1980.2, [ v, 97 p. ]

URI
http://hdl.handle.net/10203/39527
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=62713&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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