(The) effect of process parameter variation on the performance of MOS linear integrated circuit

Abstract

The importance of implementing analog circuit functions in MOS/LSI has recently been recognized. The performance of MOS linear integrated circuit is governed by the process parameters such as threshold voltage ($V_T$), junction depth($X_J$), and gate oxide thickness($T_{OX}$). In this thesis, discrete MOS transistors with different(Z/L)``s are fabricated using standard p-MOS process and the process parameters are measured. An integrated p-MOS amplifier with external compensation is designed to study the effect of measured process parameter variation on the circuit performance such as voltage gain ($A_V$), input offset voltage, cutoff frequency($f_T$), and common mode rejection ratio(CMRR) using simulation program MSINC.