(A) design of on-chip memory management unit for high speed microprocessor

Abstract

A good virtual memory management unit is essential in the design of high performance system. Main functions of memory management unit (MMU) are to convert virtual addresses to physical addresses at run time, and to enforce the protection by extracting illegal references. In virtual memory systems, the memory management hardware must also detect missing items that are not present in main memory. An on-chip memory management unit was designed supporting segmentation and paging. The segmentation unit has descriptor caches having segment translation information which allows address translation with no extra bus cycles. The paging unit has 32 TLB entries, and covers 128Kbyte memory mapping. It takes only one cycle to translate virtual address to physical address. The designed MMU was simulated in structural level with Verilog hardward description language, and some critical paths was simulated with Spice simulator. From the Spice simulation result, the MMU was proven to work well up to 40 MHz.