DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Myung-Hwan | - |
dc.contributor.advisor | 김명환 | - |
dc.contributor.author | Hwang, Woo-Sun | - |
dc.contributor.author | 황우선 | - |
dc.date.accessioned | 2011-12-14T02:14:57Z | - |
dc.date.available | 2011-12-14T02:14:57Z | - |
dc.date.issued | 1990 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=67395&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/39184 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1990.2, [ [iii], 65, [10] p. ] | - |
dc.description.abstract | Since sorting is one of the most fundamental operation in a computer system, many hardware sorters havew been developed so far. In this thesis, we present multi-functional sorting chip implemented on CAD workstation. This sorting chip, called P-TMS (Pipeline-Tree Merge Sorter), has capability of exploiting pipeline merge sorting and tree merege sorting. A sewt of the P-TMS, can organize several sorting machines such as pipeline sorting machines such as pipeline sorting machine, tree sorting machine and combined sorting machine. The combined sorting machine have configuration between a pipeline sorting machine and tree sorting machine. In case of combined sorting machine, the time complexity and number of processors become to O(n) and O($\log_2\,\gamma$) respectively, where $\gamma$ is always less than n. Especially, a number of records to be sorted are not restricted by a capacity of P-TMS but of external memory. We have designed by performing functional simulation, symbolic layout, and timing analysis of P-TMS chip with aids of GENESIL silicon compiler which can generate symbolic layout data from some higher level description. The size of the implemented in up to $1.05\times1.04 cm^2$ with CMOS2 $\mu$ n-well process technology and maximum data rate of 5.7 Mbytes/sec. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | (A) VLSI implementation of merge sort algorithm on linearly and tree connected processor arrays | - |
dc.title.alternative | Linear와 tree processor array상의 merge sort 알고리즘의 VLSI 구현 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 67395/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 000881545 | - |
dc.contributor.localauthor | Kim, Myung-Hwan | - |
dc.contributor.localauthor | 김명환 | - |
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