Mask layout generation using symbolic layout approach

Abstract

Among several methodologies developed for designing the mask layout of IC, symbolic layout approach reduces the design cycle and minimizes the design costs by alleviating the attention to be paid to keept up the design rules in layout generation. In this thesis, a Symbolic layou T EDItor called STEDI and a COmpAcTor called COAT are introduced. While STEDI, which is an interactive editing system implemented in IBM-PC with NOVA*GKS as graphics routines, produces the symbolic layout in ICDL(Intermediate Circuit Description Languages), COAT inputs ICDL data and generates the corresponding compacted mask layout in CIF(Caltech Intermediate Form). COAT solves the constraint graph with mixed constraints.