Diagnosis of register level description using fault isolation and test generation algorithm

Abstract

In this thesis we describe a diagnosis method to circuits that are described by RTLL(Register Transfer Level Language). This method is composed of two parts, namely fault isolation procedure and test generation procedure. The fault isolation procedure uses the violated expectation approach. In this step we generate the suspect list of a fault. To determine a most probable suspect among suspects, we generate tests for each suspect in the suspect list. The test generation method is similar to the path-sensitization procedure (D-algorithm). We define the behavior and control rule of the RTLL primitives to propagate values and inference through RTLL construct. And temporal logic is used to specify the digital circuits. If a fault is detected, then we can diagnose the causes of a fault by detecting the discrepancy between the actual value of the circuit and the expected value obtained from the temporal logic specification and generating tests. This system implemented by using C-Prolog in VAX/11/750.