(A) volume planner for multi-layer packing of electronic systems

Abstract

In this paper, the placement of functional blocks for 3-D IC``s and multi-layer PCB``s is studied. The initial block placement is obtained by an attractive and repulsive force method (AR method) in the three dimensional space. To match the cube, which is an analogy of 3-D IC or multi-layer PCB, with the relaxed pattern of blocks, a new algorithm is proposed. The subsequent block packing process is performed by gradual movements and rotations of blocks to minimize the chip size for each layer.