Timing yield analysis of sequential circuits considering clock network

Abstract

With the decrease in feature sizes for nanoscale CMOS technologies, the influence of process variations caused by imperfections of mask and manufacturing process becomes increasingly important. Process variations can be classified into die-to-die and within-die variations. When die-to-die variations are critical, conventional static timing analysis (STA) handles variability by analyzing a circuit at multiple process corners. However, within-die variations are becoming a non-negligible component of total variations in recent technologies. Conventional STA with within-die variations becomes very passimistic and no longer hold the conservative property. This has eventually led to Statistical static timing analysis (SSTA). Unlike combinational circuits, when considering sequential circuits in SSTA, the correlation between the combinational logic and clock network must be considered as well as the delay variation in clock network due to process variation. Our experiment shows that the correlation of clock network causes difference of the maximum timing yield from 2% to 9% in sequential circuits. However, in such that case, the timing analysis becomes more complex. We propose timing yield analysis of sequential circuits considering clock network algorithm. This algorithm handle the correlation sequential circuit due to clock network as well as the correlation of combinational circuit. Experimental results show that the proposed method provides a speedup of about 13 $\times$ on average and error of less than 1% compared to Monte Carlo simulation.