DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Seong-Hwan | - |
dc.contributor.advisor | 조성환 | - |
dc.contributor.author | Son, Woo-Kon | - |
dc.contributor.author | 손우곤 | - |
dc.date.accessioned | 2011-12-14T02:07:44Z | - |
dc.date.available | 2011-12-14T02:07:44Z | - |
dc.date.issued | 2009 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=308820&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/38700 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ vii, 49 p. ] | - |
dc.description.abstract | This thesis presents a phase detector (PD) quantization noise suppression techniques for low-noise digital phase-locked loops (DPLLs). Unlike conventional DPLLs that require high resolution time-to-digital convertors (TDCs), the proposed DPLL achieves a low-noise performance without it. First is the proportional path in the proposed DPLL is removed in order to suppress the quantization noise of the phase detector (PD). Instead, a zero is added by a sub-feedback loop around the reference phase accumulator to maintain the stability of the loop. Second is sigma-delta modulation (SDM) of division value to reduce spurious tones induced by limited resolution of a TDC. The proposed techniques do not require any precise analog or time domain circuits such as a TDC and hence can be fully synthesized without any calibration. As a result, the noise performance of the proposed DPLL is significantly improved. The proposed DPLL is theoretically analyzed and simulated in CppSim, a time-domain simulator, which shows in-band noise improvement of 10dB at in-band frequency offset. In addition, a prototype chip is implemented in 65nm CMOS process in order to verify the proposed techniques. The prototype achieves -78dBc/Hz at 10kHz offset for a 3-GHz output while dissipating 16.7mW and occupying an area of $0.16 mm^2$. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | digital phase-locked loops (DPLLs) | - |
dc.subject | quantization noise | - |
dc.subject | time-to-digital converter (TDC) | - |
dc.subject | digitally-controlled oscillator (DCO) | - |
dc.subject | modeling | - |
dc.subject | 디지털 위상고정루프 | - |
dc.subject | 양자화 잡음 | - |
dc.subject | 시간-디지털 변환기 | - |
dc.subject | 디지털 제어 발진기 | - |
dc.subject | 모델링 | - |
dc.subject | digital phase-locked loops (DPLLs) | - |
dc.subject | quantization noise | - |
dc.subject | time-to-digital converter (TDC) | - |
dc.subject | digitally-controlled oscillator (DCO) | - |
dc.subject | modeling | - |
dc.subject | 디지털 위상고정루프 | - |
dc.subject | 양자화 잡음 | - |
dc.subject | 시간-디지털 변환기 | - |
dc.subject | 디지털 제어 발진기 | - |
dc.subject | 모델링 | - |
dc.title | (A) digital phase-locked loop with phase detector quantization noise suppression techniques | - |
dc.title.alternative | 위상차 검출기의 양자화 잡음을 줄이는 방법을 사용한 디지털 위상고정루프 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 308820/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 020073257 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.contributor.localauthor | 조성환 | - |
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