Design of processing element and memory for pre-processing of object recognition

Abstract

Recently, Object recognition has been applied to many fields such as vehicle detection, robot vision and face recognition. It is the process of identifying pre-learned object from input video scene in real-time. Object recognition can be divided into two stages, pre-processing which extracts feature points from image and post-processing which matches feature vector with database. In this work, SoC design for pre-processing of object recognition is presented. High-level modeling is performed by unified modeling language (UML) for system improvement. Based on the model, required data transactions and computations of each pre-processing operation are analyzed. As a result, it is proved that gaussian filtering and finding local maximum address operation are two computational bottlenecks of the system. To resolve these, processing element and memory are designed in customized hardware block. Processing element, a kind of 32-bit RISC processor, is designed to accelerate gaussian filtering operation. Sum of dot products (SDP), load extension (LE) and division (DIV) instruction are newly added and SIMD and logarithmic fashion are exploited in datapath. Limited in image filtering operation, performance of processing element is improved about 8.3 times compared to that of general purposed processor. Memory is designed to have a special feature of finding local maximum address in 3x3 window. It includes additional peripherals and micro logics to achieve this in memory. As a result, finding local maximum address in 3x3 window can be performed in a single cycle and this reduces the cycle time to complete finding local maximum address operation dramatically. In SoC, 10 PEs and 8 memories are integrated in the area of 7.5um x 5.5um. For functional verification of designed pre-processing stage, it is implemented on FPGA board. A real chip implementation is now being progressed in TSMC 0.18um process.