Real-time trace for performance analysis in OR1200

Abstract

The most popular method of software debugging in hardware like FPGA or Silicon chip is start/stop method using JTAG. However, there are some cases that it is impossible to use start/stop method both in real-time systems and non-real-time systems. To cover these cases, software engineers use real-time trace. Until a several years ago real-time trace was only available using a Logic Analyzer or In Circuit Emulators. These tools were expensive and difficult to use. Also, as processors became more complex and more deeply embedded, it became less and less practical to make the signals required to make trace be connected in processor. In the last few years many embedded processors have included on chip trace unit. ETM(Embedded Trace Macrocell) of ARM processor and IEEE-ISTO Standard Nexus5001 are representative. Until now the use of real-time trace is focused on the software debugging. Performance analysises for software optimization have been provided by co-simulation tools. This thesis proposes the method to support performance analysis of software by real hardware using real-time trace. This method is more accurate and faster than co-simulation tools. Cycle accurate performance analysises can be used at software development where cycle count is very critical. To support performance analysis and debugging features we designed a new trace specification. And we propose some new methods to decrease the generation speed of trace and to reduce area size of real-time trace unit. We verified all tracing system in FPGA using iNCITE board. Experimental result shows four kinds of performance analysises in GUI.