Analysis and design of time-based analog-to-digital Converter using ring voltage-controlled oscillator

Abstract

Voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture of which time resolution is improved by fast digital transition time from technology scaling. In this paper, we describe the analysis of non-idealities such as jitter, nonlinerity and mismatch of VCO which limit the performance of VCO-based ADC. The digital calibration method is briefly described to enhance SFDR from the nonlinearity of VCO characteristic. The design consideration for sampling rate and quantization method and the optimization of designing reconfigurable ADC is also represented. These are implemented and verified using CMOS 0.13um technology. The implemented architecture utilizes 64 phase ring VCO considering one-bit quantization for 500MHz sampling clock and achieves reconfigurable property whose SNR is 72dB to 35dB for 100kHz to 250MHz input bandwidth. The power dissipation of designed ADC is 12.5mW and 0.95pJ/step of FOM can be achieved.