Modeling and verification of power/ground noise generation and coupling in CMOS feedback operational amplifier반환 회로 연산 증폭기에서의 전력/접지 잡음의 생성과 회로와의 결합에 대한 모델링과 검증
Recently, importance of SiP is emerged to implement a system which has low power consumption and a small size because of low manufacturing cost, short time to market and high IP reusability. The SiP of the mixed mode system has a problem that power/ground noises from other chips flow into analog circuits, which makes system malfunctions. The operational amplifier is one of the most important circuits composing an ADC or a DAC. If noises flow into the op amp, the output offset voltage is generated, which makes wrong outputs of ADC or DAC.
In this paper, effect of power/ground bounce noises on the operational amplifier is analyzed and models of the package, chip and circuit are proposed to analyze the DC output offset voltage of the op amp. It is very difficult to expect the output offset voltage of the op amp without estimation of noises. In a practical case, the noises from outside of the chip change to the noises which have other amplitude and phase since the noises pass through capacitance and inductance of the package and chip PDN. In this paper, power/ground distribution network of the package and chip are modeled in lumped elements to extract noises flowing into the circuit. And the equivalent circuit model is proposed to analyze the DC output offset voltage by power/ground bounce noises. We can expect the output offset voltage using these models.