Skewed flip-flop transformation for minimizing leakage in sequential circuits

Abstract

Mixed $V_t$ has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elements, such as flip-flops, contribute an appreciable proportion of the total leakage. A skewed flip-flop (SFF) is obtained by slightly increasing the gate length of a subset of the transistors in a conventional flip-flop. The resulting SFF will exhibit very skewed characteristics in terms of leakage and delay, which depend on the transistors that are replaced. We present an algorithm that selectively substitutes SFFs for conventional flip-flops in sequential circuits, such that the timing constraint is still satisfied while the leakage from the flip-flops is reduced. When combined with the mixed Vt technique, an average leakage saving of 17% is achieved, compared to the use of mixed $V_t$ alone. The leakage of the flip-flops themselves is cut by 56% on average.