Investigation on multi-gate FinFETs by using 3-dimensional device/mixed-mode simulation

Abstract

Due to the challenges with scaling planar bulk MOSFETs, multiple-gate MOSFETs (e.g., FinFETs) are expected to be eventually implemented. To antedate and exploit the advanced MOSFETs technology, novel application of multiple-gate MOSFETs for 2-bit non-volatile memory is suggested and verified with 2-D simulations. Gate misalignment effects on DC/AC characteristics of triple-gate FinFET are studied with aid of 3-D mixed-mode simulations. The 2-bit operational non-volatile memory based on asymmetric double-gate FinFETs are proposed and successfully demonstrated for its reliable 2-bit operations. The newly proposed 2-bit non-volatile memory can be fabricated by disconnecting both sidewall channels with CMP process. For reliable 2-bit operation, the device parameters of tunneling oxide thickness and gate workfunctions are optimized and programing/erasing/reading methods for uniform V¬T distribution and large window margin are studied with the aid of 2-D device simulations of ATLAS $Silvaco^®$. Mixed-mode simulation was extended to consider 3-dimensional geometric shape of highly scaled planar devices, and advanced devices like FinFETs. By exploiting newly developed 3-dimensional mixed-mode simulator, gate misalignments effects in FinFETs are studied. The condition for minimizing parasitic resistances is critical to reduce the RC delay in SOI FinFET, while drain diffusion capacitance is main degrader for RC delay in the body-tied FinFET.