(An) implementation of VHDL simulation system using compilation technique

Abstract

Simulation is a very important phase in digital system design. Today VHDL widens its area in the design field and a lot of VHDL simulator is emerging. Most of commercial simulation tools use the compilation technique for high speed simulation. Because those tools generates machine codes directly to obtain the highest performance, they are highly dependent of operating systems. In this thesis work, a VHDL simulation system called VS using the compilation technique was implemented in the UNIX environment. Since this system generates standard C programs, it can be ported to other operating systems with ease. From the testing through simulation of two circuits in VHDL -- one in structural level and the other in behavioral level -- it is proved that the simulator works correctly. This work has focused heavily on the correct functionality of the implemented simulator so that the the optimization for speed up has not yet been fully considered. Nevertheless the simulation speed of VS is 7 to 8 times faster than that of Quicksim -- the VHDL simulator of the Mentor Co. -- on the behavioral level benchmark. For the structural level benchmark the performance is poor-about 10 times slower than Quicksim.