Design and implementation of Mesh Wormhole Router

Abstract

Conventional message passing multicomputers use store-and-forward routing networks and the message transmission time is linearly proportional to the distance of a message transfer, which results a large overhead in interprocessor communications. To overcome those disadvantages, wormhole routing mechanism was proposed, and it is considered as the most promising technique from the view point of the hardware design and the message transmission time which is additive to the distance of a message transfer. In this thesis, the details of the design and implementation of a wormhole router chip for 2-dimensional mesh-connected multicomputer are described. The wormhole router design is described with VHDL and its logical operation is verified by extensive simulations. The designed wormhole router is implemented using FPGAs(Field Programmable Gate Arrays), XILINX XC3090-PG175. To demonstrate its real operation, 4 node computers and 4 FPGA mesh wormhole routers are interconnected by 2 x 2 mesh. For interconnecting the routers, a routing board containing 4 FPGA wormhole routers is developed. Several communication primitives are programmed and added to the existing kernel of our own parallel computer, K860/32. The implemented wormhole router operates successfully at 5 MHz clock frequency, and the maximum bandwidth of 20 Mbits/sec is achieved between communicating nodes. The final goal of our wormhole router is the fabrication of a VLSI wormhole router chip with higher operating frequency, higher bandwidth and wider channels. For an advanced VLSI wormhole router, several design problems and advanced aspects are discussed based on current implementations.