Design of cache controller and bus unit for K486 microprocessor

Abstract

In this thesis, Cache, cache controller and bus interface unit for 32-bit microprocessor, K486 which is a instruction-level compatible CPU with Intel $i486^{TM}$ have been designed and simulated for each typical cycle, most of the description is done in structual level by verilog hardware description language. By on-chip MMU and on-chip cache, system-level address translation overhead and external memory access bottleneck has been removed. This make it possible to execute a simple instruction only in one clock reducing pipeline stall. Special features, for example line buffer, and write buffer, and reordering, have been devised for the performance of overall chip. By these feature concurrent operation of interanl pipeline and external bus cycle is possible. All these features are aimed at the reducing the pipeline stall. External bus was devised featuring burst data transfers to quickly fill cache lines and provisions to insure multiprocessor cache coherency and bus locking, and various operand size supporting cycle like as pseudo lock cycle.