Exploiting the Inherent Parallelisms of Back-Propagation Neural Networks to Design a Systolic Array

Abstract

In this paper, two-dimensional systolic array for back-propagation neural network is presented. The design is based on the classical systolic algorithm of matrix-by-vector multiplication, and exploits the inherent parallelisms of back-propagation neural networks. This design executes the forward and backward passes in parallel, and exploits the pipelined parallelism of multiple patterns in each pass. The estimated performance of this design shows that the pipelining of multiple patterns is an important factor in VLSI neural network implementations.