Combined image signal processing for CMOS image sensors

Abstract

This thesis presents a new design of a digital image signal processor developed for CMOS image sensors. CMOS image sensors (CISs) have various benefits compared with charge-coupled devices (CCDs), though the image acquired from a CIS has lower quality than that from a CCD. In order to enhance the quality of CIS images, it is required to do enhancing and reproducing processes such as color demosaic, white balance, color correction, gamma correction, and color conversion. In conventional designs [7-10], these processes are implemented separately. In this thesis, a combined image signal processing is proposed, which merges several image processes such as color correction, white balance, and color conversion into a single processing. Also it reduces three gamma correction blocks into one block, leading to reduce hardware area and power consumption. The proposed image processor has the comparable performance to enhance and reproduce images compared with a conventional. The proposed image processor is implemented by Verilog-HDL and synthesized with CMOS 0.18um standard cell library. In results, it reduces the hardware area by 23.8% and the power consumption by 10% compared with a conventional.