(A) 250MHz - 2GHz wide range delay-locked loop

Abstract

This work describes a delay-locked loop which guarantees the reliable operation without false lock in wide frequency range. A proposed operation algorithm and an improved phase detector widen considerably the operating frequency range of the DLL. A new circuit ‘Pulse Reshaper’ provides a simple and efficient scheme for lock detection. It also alleviates quite the problem of static phase offset by the current mismatch of charge pump. In the proposed DLL, because variable delay range of voltage-controlled delay line is comparatively narrow, the DLL can keep a fine tuning despite its wide operating range. Furthermore, the proposed phase detector improves the locking speed of the DLL. The proposed DLL practically has a short locking time after power-up since it has no initial circuit and reset(or enable) signal for correct operation. The proposed DLL is designed in TSMC 0.18um process. The area of core part(except for IO part) is 230um*200um. The DLL operates in wide frequency range from 250MHz to 2GHz. The amount of skew between reference clock and output clock is less than 10ps in most frequency range. The DLL has a rms jitter of 2.9ps and a peak-to-peak jitter of 17.4ps at 2GHz.