Storage offset assignment for execution time improvement in digital signal processor

Abstract

DSPs typically provide indirect addressing mode with auto-increment and auto-decrement, which provide efficient address arithmetic calculations to access automatic variables. The code size of the generated code can be effectively improved by auto-increment or decrement addressing mode in DSPs, thereby reducing the entire amount of address arithmetic instructions. The utilization of such an addressing mode is sensitively dependent on the placement of variables in storage. So finding proper optimal placement of variables in memory called storage offset assignment is a very important problem in the field studied by many researchers. The result of the storage assignment depends on the access sequence and its access graph model. Storage offset assignment by previous researcher presents a good formalism of the problem of optimal storage assignment for a basic block, but lacks the exact model for a procedure. Its model also ignores the access patterns between the basic blocks and only uses the static weight for code size reduction. This paper proposes a better access graph model by considering the control-flow dependent access sequence more carefully in boundary between the basic blocks. It also proposes a more accurate weight model with the dynamic behavior of access patterns. Experimental results for DSPStone, ADPCM and G721 show 6.43% improvement on the average over the native storage assignment and even 12% for ADPCM.