Model checking using interface abstraction인터페이스 추상화를 이용한 모델 체킹

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This thesis presents a methodology of formal verification using model checking tool. Model checking is used to determine the validity of formulas written in temporal logic to respect the behavioral model of a system. One of the serious limitations of the model checking approach comes from its reliance on the explicit state transition graph representation of the hardware system to be verified. Typically, the number of states increases exponentially with the number of elements in the system, resulting in what is popularly called the state explosion problem. Although many researchers have tried to verified solved this problem using the abstraction and reduction of the environment and target system, no general and explicit methodology for the abstraction of the environment has been presented yet. The proposed method in this thesis tries to solve the state explosion problem in the model checking is based on ‘design separation’ and ‘interface abstraction’. Design separation is a process separating the whole design into small designs to be verifiable while the interface abstraction is a process for modeling the interface behavior between separated designs. By means of this method the complex design having a state explosion problem can be verified successfully and the memory usage and computing time for model checking also can be improved about 100 times than no use of the proposed method.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2003
Identifier
180509/325007 / 020013570
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ iv, 44 p. ]

Keywords

abstraction; verification; formal verification; model checking; interface; 인터페이스; 추상화; 검증; 형식검증; 모델체킹

URI
http://hdl.handle.net/10203/37674
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=180509&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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