Implementation of synchronization barrier for multiple interface blocks in data-intensive applications

Abstract

This thesis describes a design of the barrier to synchronize interface protocol blocks in data-intensive application and implements it to behavioral emulator as the typical example of the data-intensive application. Behavioral emulator has interface protocol block to communicate the target system. As target system is more complex, synchronization for interface protocol blocks is more required. Using the barrier synchronization for interface protocol blocks, behavioral emulator can use the multiple FPGA with fully scalability. This is useful because target system can require more I/O to behavioral emulator. Specialized hardware is often used to improve the performance of a barrier synchronization operation. The proposed barrier hardware is customized to behavioral emulator. The barrier hardware has been implemented in behavioral emulator and verified by gate-level simulation.