Co-simulation based system performance analysis using SystemC

Abstract

The rapid improvement on silicon process technology allows a complex system to be integrated onto a single chip. This revolutionary System-on-Chip (SOC) paradigm enables unprecedented performance and functionality at a low cost, using the benefit of small size, low power consumption, etc. On the other hand, due to the increased scale and complexity of the target system, designing optimized architecture from the functional specification is becoming more and more difficult. Therefore simulation based performance analysis is the efficient method for the SOC design. In this paper I present a fast system performance analysis method based on co-simulation using SystemC. As concurrent operations between hardware and software increase, the I/O access latency caused by shared bus and memory contention affects entire system performance. I explained noble simulation framework that has timing information directly annotated from the commonly used high level functional specification method such as C/C++ with the help of SystemC. The simulation speed is only hundreds times slower than that of untimed functional execution, and the designer is offered good chances to examine how the architectural decision alters overall system performance rapidly. For designers to use our simulation framework conveniently, I addressed system component templates and tools for using these templates. Using the example of ADPCM and printer system, the efficiency and accuracy of our approach are tested, resulting in very similar behavior to the real system.