In this paper, we firstly present the high frequency equivalent circuit model of Wafer Level Package (WLP) interconnection up to 5 GHz. Since WLP interconnection is fabricated on the semiconductor, it can be compared with on-chip MIS transmission lines. But the dimension of the WLP interconnection, such as thickness of dielectric layer and metal line, is much larger than that of the on-chip interconnection. Previous studies about MIS structure cannot be applied directly to WLP interconnection. The thick dielectric layer and on-chip metal plane in the WLP interconnection result in relatively low slow wave factor. Measurement results, along with the quite low loss, confirm operation in a quasi-TEM mode in the WLP interconnection. The extracted model parameters from measured S-parameters are compared with theoretical results on several such structures. Excellent agreement is found, which shows WLP interconnection can be regarded as conductor-backed coplanar waveguide with silicon losses. Finally, based on the extracted model parameters, we simulated the signal integrity of Rambus Memory Module when WLP is applied. And successfully demonstrated that the increased capacitive loading of WLP can be compensated by choosing proper line impedance.