(A) new CMOS passive mixer with high linearity for low power transceiver

Abstract

A conventional CMOS passive ring mixer, which consists of four NMOS switches, is suffered from output compression due to threshold voltage drop problem of NMOS switches. To overcome this problem, we proposed a new CMOS passive ring mixer that consists of four NMOS and four PMOS switches. Additional PMOS switches are in parallel with NMOS switches. The proposed mixer is implemented using 0.25um CMOS process. It shows the voltage conversion gain of -1.36dB, P1dB of 2dBm, IIP3 of 12.5dBm, LO to RF isolation of 41.2dB, and die area of 0.14㎟.