Design of a low power MP3 decoder

Abstract

MPEG-1 audio layer III, commonly called MP3, is one of the most widely used audio compression standards. As the computation power of portable devices, such as PDA’s or smart phones, grows, MP3 playback became a basic function to be equipped with, but MP3 decoding is a data-intensive application and, thus, expensive for such devices since power consumptions is a critical problem. This thesis presents a low power MP3 decoder. The presented MP3 decoder is a RISC DSP suited for MP3. Approaches to achieve low power are taken in algorithmic and architectural level. Those are fixed-point arithmetic-based implementation, reduced bitwidth of registers and memory, and cycle count reduction for lower operating frequency using a new set of instructions. Various examination and experiments on the decoding algorithm are carried to exploit the characteristics in low power implementation. The resulted cycle count per frame is so small that it can operate with 12.8 MHz while decoding in real-time, which is the second lowest among similar previous implementations and the lowest among the commercial products. The product of this thesis is a synthesizable Verilog HDL code in RTL level.