Low power architecture of discrete wavelet transform using pseduo circular cache

Abstract

This paper addresses a new method of reducing power dissipation in discrete wavelet transform(DWT), which is consisted of finite impulse response(FIR) filters. As the wireless image communication is very rapidly advanced, power becomes one of the major topics in implementation of DWT algorithm because FIR filters have many multipliers. Fortunately, we can exploit the spatial redundancy of images in order to reduce power in multiplication. The higher n-bits of adjacent pixels are not almost changed so that the computation in multiplier can be separated to higher n-bits and lower m-bits multiplication in (n+m) x coefficient. And the result of higher n-bits multiplication is stored in memory such as cache. When the higher n-bits of current pixel are contained in TagRAM of cache, the redundant multiplication can be avoided by using the previous calculated values. The new architecture applied this idea is proposed in this thesis. The optimized memory size and tag bit width are determined by high-level language such as C and verified with Verilog-XL simulator. The power distribution of multipliers in FIR filters is about 80% ~ 90%. Therefore we can reduce power in DWT Filter modules about 15% using separated multiplication techniques. Also the performance is increased to 20% because the smaller multiplier is used. However, the area is increased about 20% for inserting memory such as cache and additional hardware components.