Design of a low power floating point adder

Abstract

The demand for high performance, low power floating point adder cores has been on the rise during the recent years. These units are essential building blocks of microprocessors and floating point DSP data paths. Since the hardware implementation of floating point addition involves the realization of a multitude of distinct data processing sub-units that endure a series of power consuming transitions during the course of their operations, the power consumption of floating point adders are, in general, quite significant in comparison to that of their fixed point counter parts. Owing to the presence of a relatively high traffic of floating point additions in micro-processors and DSPs, the power/performance implications of floating point adders, directly impact the power/performance desirability of the target application. In this paper, we present an architecture of a low power floating point adder. The functional partitioning of the adder into four distinct, inhibit controlled data paths allows activity reduction. The proposed scheme offers 14% reduction in power consumption in comparison to that of the conventional triple data path.