Algorithms for minimizing the delay and the number of adders in FIR filter design

Abstract

Area, power, and speed are major factors in implementing digital filters. In the case of fixed-coefficient filters, common subexpression sharing has an important role in reducing the area and power and has been studied by Bull and Horrocks, Dempster, Hartley, Potkonjak, and so on. In this paper, we find misses of the previous methods and propose two modified algorithms. One is to reduce area and the other is to increase speed. To reduce area, we consider minimal signed digit representation(MSD) as well as canonical signed digit representation(CSD) and the loss in the middle of algorithm as well as the profit. The number of adders is reduced by about 3\%. To increase speed and meet a given speed specification, we use the tree reduction method and the limited-selection method. The number of adder stages required to produce coefficients is reduced to about half with overhead less than 15\%. In order to generate digital filters automatically, we make a filter HDL code generator. This generator takes information about the structure of filters and generate HDL code considering the structure for carry-save adder(CSA).