New HDL for synchronus digital system and simulator implementation

Abstract

Most digital VLSI designs are synchronous and the two most important issues in the design are to enable fast simulation and stable synthesis. Verilog-HDL and VHDL are widely used languages for hardware description . However they have drawbacks in terms of synthesis since the synthesis is not considered when the languages were defined. Thus, in this paper we suggest a new hardware description language which is adequate for synchronous digital systems. The new HDL is defined with assuming that only hardware part to be synthesized is described using it and all other components related to simulation are modeled in C language. Since the hardware description is positioned at the middle of synthesis and simulation, we can eliminate most of the design bugs that are caused by mixed use of synthesis semantics and simulation semantics. We also developed a translation tool converting the hardware description into levelized C functions which are used to make compiled-code simulator. The customized simulator runs 2 to 7 times faster than the fastest commercial simulator.