(A) design of low-power CMOS microcontroller core for portable systems

Abstract

The recent growth in portable systems that require a large amount of control processing demands a microcontroller with both high performance and low power dissipation. Since the memory in microcontroller systems dominates the total power dissipation, it is very important to design a microcontroller that reduces memory accesses as well as the power dissipated by the microcontroller itself. This thesis suggests a RISC microcontroller core architecture, which minimizes memory data transfer by employing an efficient 16-bit fixed length instruction set and by allowing data to be transferred in 8-, 16-, or 32-bit size for load/store instructions. Many other low-power design techniques that have been proposed by previous works are also introduced in it. The impacts of the new instruction set architecture on power reduction are evaluated by comparing the instruction count of Dhrystone 1.1 code with those of other microcontrollers. Comparing the estimated capacitance of the synthesized decode circuit with the capacitance associated with memory transfer reveals that the additional decoding overhead is not so great against the gain in code size.