(A) design of floating-point unit for low-power processor

Abstract

This thesis describes a pipelined floating-point unit(FPU) for a low-power processor. The goal of this design is to achieve a low-power design and an area-optimized implementation, as it will be integrated on a single chip with a low-power processor core. It consists of two major functional units, floating-point arithmatic logic unit (ALU) and floating-point multiplier/divider(MULDIV) unit. It supports both single precision format data and double precision format data. To reduce the required power, the upper half part of datapath is disabled when calculating the single precision data. Many parts of the FPU are shared to reduce the area. For example, multiplier and divider uses the adder in ALU, and ALU consists of only one shifter and one adder, needs less area than conventional ones.