DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Beom-Sup | - |
dc.contributor.advisor | 김범섭 | - |
dc.contributor.author | Lim, Kyoo-Hyun | - |
dc.contributor.author | 임규현 | - |
dc.date.accessioned | 2011-12-14T01:41:00Z | - |
dc.date.available | 2011-12-14T01:41:00Z | - |
dc.date.issued | 1997 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=115077&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36985 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1997.2, [ v, 45 p. ] | - |
dc.description.abstract | This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications. Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | Optimum loop band-width design for low noise PLL application | - |
dc.title.alternative | 저잡음 PLL 응용을 위한 최적의 루프 대역디자인 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 115077/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 000953505 | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.localauthor | 김범섭 | - |
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